AI PCB Design: A Constraints Guide for Engineers

Why constraints are the whole job

In manual routing, constraints live in three places: the design rules dialog, the schematic notes, and the layout engineer's head. The third bucket is the dangerous one — undocumented intent that only surfaces in review. AI PCB design forces that tacit knowledge out into the open. If the engine doesn't see a constraint, it doesn't exist.

The good news: once your constraints are explicit, a generative router can produce a DRC-clean board in minutes and re-run on every spec change without re-doing manual work. The cost of writing them down once is paid back on the first iteration.

1. Board outline and stack-up

Start with the physical envelope. The engine needs a closed outline, layer count, and dielectric stack — not a vague "4-layer board, about 50 × 80 mm."

• Outline: exact polygon in mm (or mils — pick one unit and stay there). Include any cut-outs and mounting-hole keep-outs.
• Layer count and order: e.g. SIG / GND / PWR / SIG for a 4-layer board. State which layers are signal, plane, or mixed.
• Dielectric stack: core and prepreg thicknesses, copper weights (½ oz / 1 oz), target finished thickness. This is what the engine uses to compute impedance.
• Finish and mask: ENIG / HASL, soldermask and silkscreen colors — these don't affect routing but they belong in the same constraint document so the fab package is self-contained.

2. Clearance and width rules

Clearance and trace-width tables are the bread and butter of any router. For a generative engine, write them as a matrix, not as "we usually do 5 mil."

A quick unit reminder for engineers crossing tool boundaries: 1 mil = 0.0254 mm. A 5 mil trace is 0.127 mm; a 10 mil clearance is 0.254 mm. Pick one unit for the whole constraint document and stick to it — mixed-unit tables are the single most common source of router-side errors.

3. Impedance and high-speed nets

For anything above ~50 MHz, the engine needs explicit impedance targets, not just "route as diff pair." Specify per net class:

• Single-ended impedance: target Ω and tolerance (e.g. 50 Ω ±10%).
• Differential impedance: target Ω, tolerance, and intra-pair skew budget in ps or mm (e.g. 90 Ω ±10%, skew < 5 ps).
• Length matching: per group, with the reference net and tolerance — not just "match DDR_DQ[0:7]."
• Return path: which reference plane each high-speed net rides over. If a net has to change reference, state where stitching vias are required.

4. EMI and isolation envelopes

EMI rules are usually the most underspecified constraint. A manual layout engineer "knows" to keep the switcher away from the ADC; a generative engine needs that as a hard rule. Define:

• Keep-out regions around switching regulators, antennas, and crystals (as polygons, with min clearance to specific net classes).
• Forbidden layer pairings — e.g. no high-speed routing directly under the radio module footprint.
• Shield can footprints and the nets they must enclose.
• Ground-pour rules: solid vs hatched, stitching via pitch around the board edge, and around high-speed nets.

5. Mechanical and assembly constraints

• Mounting holes: position, diameter, and keep-out radius for both copper and components.
• Connector positions: fixed XY for any connector that mates with an enclosure or another board — the router treats these as locked.
• Component height zones: max Z by region, for enclosures with internal ribs or heatsinks.
• Assembly side: which side(s) carry SMT, which carry through-hole, and whether the board is wave- or reflow-only.
• Fiducials and tooling: three fiducials minimum, plus panel rails if you're providing them.

A minimal constraint template

When you're starting a new board with an AI router, a single file with the following sections is usually enough to get a first-pass layout. Treat it as a checklist:

# Board
outline_mm: [...]
layers: 4
stackup: SIG / GND / PWR / SIG
finished_thickness_mm: 1.6

# Rules (mil)
default: { width: 5, clearance: 5, via: 10/20 }
power_3A: { width: 40, clearance: 10 }
diff_90:  { impedance: 90, tol: 10%, skew_ps: 5 }

# Keep-outs
switcher_zone: polygon, min_clear_to=analog 50mil
radio_module: no high-speed under footprint

# Mechanical
mounting_holes: [(x,y,d,keepout)...]
fixed_connectors: [(ref, x, y, rot)...]
max_height_zones: [...]

The IDO take

The shift from manual to AI PCB design isn't about giving up control — it's about moving control upstream. Instead of expressing intent by pushing traces around at 2 a.m., you express it once, in the constraint set, and let the engine produce the board. The engineers who get the most out of generative routing are the ones who treat the constraint document as the real design artifact.

If you want to see this loop in practice, CircuitGen is the IDO platform that consumes a constraint set like the one above and returns a routed, DRC-clean board. For a broader comparison with manual workflows, see AI PCB design vs manual routing.