RL vs Physics Solvers: Testing Quilter and DeepPCB on Mixed-Signal Boards

We tested DeepPCB and Quilter on dense 6-layer mixed-signal layouts to see how pure RL topology agents compare to physics-guided constraint engines under real EMI rules.

Route a 6-layer mixed-signal board with a switching regulator, a high-speed microstrip bus, and a 24-bit delta-sigma ADC by hand, and you will spend four full working days adjusting traces. Hand-routing every non-critical signal on an STM32MP1 or an i.MX8 board is tedious, but conventional autorouters from the Specctra era usually turn your ground planes into Swiss cheese.

Two different paradigms have emerged to solve this problem with modern compute. DeepPCB uses reinforcement learning agents trained primarily on board topologies and geometric routability. Quilter takes an alternative path, wrapping generative routing inside deterministic electromagnetic and circuit-level physics solvers, including an integration with Simberian's Simbeor field solver.

We ran both engines through a battery of high-density mixed-signal test layouts to see how their underlying algorithms handle signal return paths, ground plane slotting, differential pairs, and decoupling loops. If you run a small hardware team or carry the entire EE workload at your company, knowing where these tools succeed and where they ruin your electromagnetic compliance (EMC) profile dictates whether you save three days or waste three thousand dollars on an unnecessary board spin.

The Fundamental Architectural Split

Traditional autorouters treat PCB routing as a maze-solving problem. They run variants of Dijkstra's algorithm, Lee's maze router, or A* search on a discretized grid. These algorithms know what a design rule check (DRC) violation is because the CAD system enforces clearance boundaries, but they have no intrinsic concept of return path inductance, parasitic capacitance, or RF radiation loops.

Modern automated routers diverge into two camps based on how they evaluate success.

+-------------------------------------------------------------+
|                      CAD / Netlist Input                    |
+-------------------------------------------------------------+
                               |
        +----------------------+----------------------+
        |                                             |
        v                                             v
+-------------------------------+             +-------------------------------+
|       DeepPCB Approach        |             |        Quilter Approach       |
| (Topological RL Engine)       |             | (Physics-Grounded Solver)     |
+-------------------------------+             +-------------------------------+
| - Graph neural nets & MCTS    |             | - Circuit-aware placement     |
| - Geometric reward functions  |             | - Simbeor field solver engine |
| - Optimizes: completion rate, |             | - Physics scorecard validation|
|   trace length, via count     |             | - Optimizes: loop inductance, |
| - High routing throughput     |             |   impedance, return paths     |
+-------------------------------+             +-------------------------------+

DeepPCB models the PCB as an environment for a reinforcement learning agent. The agent receives rewards for completing net connections, minimizing total trace length, avoiding DRC clearance errors, and reducing via count. This enables impressive topological flexibility. DeepPCB routes complex digital boards rapidly, frequently achieving complete connectivity with fewer vias than a junior layout engineer. However, its core agent evaluates geometric success rather than electromagnetic field distributions. Unless a physical constraint is strictly translated into a hard geometrical boundary box or keepout, the agent does not intrinsically understand that a trace running over a split ground plane radiates RF energy.

Quilter grounds its routing pipeline in deterministic physics validation. Instead of treating the schematic simply as a netlist of point-to-point connections, Quilter extracts circuit-level context. It identifies bypass capacitor loops, switching regulator topologies, and differential pair relationships before a single trace is pulled. During generation and post-route evaluation, candidate solutions are scored against a physics engine that runs numerical checks, including transmission line impedance calculations via the integrated Simbeor 2.5D/3D field solver. The engine prioritizes electromagnetic integrity over purely geometrical routing shortcuts.

Understanding this difference explains why both engines can produce complete, DRC-clean boards that behave completely differently when powered up in an RF chamber.

Test Setup: The 6-Layer Mixed-Signal Benchmark

To evaluate both engines, we used a standard 6-layer high-density interconnect (HDI) stackup. This configuration reflects the standard mixed-signal board produced by startups building edge devices, industrial controllers, or robotics compute modules:

Layer 1 (Top): High-speed signals, RF microstrips, critical analog components, discrete passives.
Layer 2 (GND01): Unbroken reference ground plane (0.5 oz copper, 0.1 mm prepreg to Layer 1).
Layer 3 (SIG01): Low-speed digital signals, SPI, I2C, control lines.
Layer 4 (PWR): Split power planes (+3.3V, +1.8V, +5V, +12V rails).
Layer 5 (GND02): Secondary continuous ground return plane.
Layer 6 (Bottom): Mixed low-speed routing, debug headers, bulky connectors, secondary power traces.

The benchmark design included four distinct problem areas that stress automated routing engines:

A high-precision analog front-end (AFE): A 24-bit ADC reading low-amplitude sensor inputs, requiring low parasitic capacitance and total isolation from digital switching noise.
A synchronous buck regulator: A 12V-to-3.3V step-down stage switching at 2.2 MHz, featuring high dI/dt loops and a noisy switch node (SW) carrying steep dV/dt transitions.
High-speed differential digital lines: USB 2.0 High-Speed (480 Mbps) data lines requiring 90-ohm differential impedance, paired with 50-ohm single-ended high-speed SPI buses.
A high-pin-count BGA microcontroller: A 0.8 mm pitch controller requiring clean breakout channels without destroying the reference ground layer directly underneath.

Let us look at how both approaches performed across each domain.

Ground Plane Integrity and Return Current Paths

Every high-speed signal is an electromagnetic wave whose energy travels in the dielectric between the trace and its reference plane. The return current flows on the path of least impedance directly underneath the trace at frequencies above roughly 100 kHz. When an autorouter cuts a slot into a ground plane by clustering vias too closely or by dropping traces across reference plane splits, the return current is forced to detour. This turns a simple signal trace into an efficient loop antenna.

POOR (DeepPCB unconstrained via cluster creates a return path slot):
Layer 1: ================= Trace A ================>
Layer 2: [ GND Copper ] (Via) (Via) (Via) (Via) [ GND Copper ]
                        <---- Void Slot ---->
               Return current forced around void (High EMI)

CONTROLLED (Quilter physics engine staggers vias to preserve copper):
Layer 1: ================= Trace A ================>
Layer 2: [ GND Copper ] (Via) [Copper] (Via) [ GND Copper ]
         ----------------- Continuous Return Path ----------->

DeepPCB's Return Path Behavior

DeepPCB routes with remarkable speed and achieves dense trace packing, but it treats reference planes primarily as available routing channels or clearance zones unless hard-coded copper keepouts are manually created by the designer.

In our dense BGA breakout zone, DeepPCB grouped through-hole vias in linear rows with standard 0.2 mm hole-to-hole clearances. While this satisfied the manufacturing DRC rules from the fab house, the overlapping antipads removed a 6 mm strip of copper on Layer 2 directly under two high-speed digital lines running on Layer 1. The return current for those traces was forced to divert around the perimeter of the via field, creating an inductive loop area of roughly 18 square millimeters.

When routing digital lines on Layer 3, DeepPCB frequently referenced Layer 4 (power) without checking if the trace crossed the boundary between the +3.3V and +1.8V split copper zones. The traces crossed these plane splits repeatedly. In a real-world test, this causes severe ringing, impedance discontinuities, and significant common-mode radiation.

Quilter's Return Path Behavior

Quilter avoided plane-splitting errors by evaluating candidate routes against ground-plane continuity metrics. In the same BGA breakout area, Quilter's solver staggered via placements, preserving unbroken copper webs between adjacent antipads on Layer 2.

When Layer 3 routing was necessary, Quilter prioritized referencing Layer 2 (GND) over Layer 4 (PWR). When signals crossed split power regions on Layer 4, the solver automatically dropped stitching ground vias adjacent to signal layer transitions, ensuring that return currents could bridge the reference change without circulating through distant decoupling capacitors. This behavior keeps the return loop small and prevents electromagnetic interference problems before the board ever reaches an anechoic test chamber.

Differential Pair Matching and Impedance Control

Differential signaling relies on two tightly matched traces carrying equal and opposite currents. While coupling between the two traces is helpful, the primary function of the pair is maintaining constant differential impedance and equal propagation delay while referencing a solid ground plane.

Routing Metric	DeepPCB (Pure RL Topology)	Quilter (Physics-Guided Solver)	Target Requirement
USB 2.0 D+/D- Length Match	$\Delta L = 3.42\text{ mm}$ (Failed)	$\Delta L = 0.18\text{ mm}$ (Passed)	$\Delta L < 0.5\text{ mm}$
Differential Impedance ($Z_{\text{diff}}$)	$74,\Omega - 108,\Omega$ (Unstable)	$90.2,\Omega \pm 2.1,\Omega$ (Stable)	$90,\Omega \pm 10%$
Reference Plane Transitions	4 transitions, 0 stitch vias	2 transitions, 2 stitch vias	$\le 2$ transitions with GND stitch
Phase Skew	$22.8\text{ ps}$	$1.2\text{ ps}$	$< 5.0\text{ ps}$
Uncoupled Length around Obstacles	$14.2\text{ mm}$	$2.1\text{ mm}$	Minimize

DeepPCB Results

DeepPCB managed to connect the USB 2.0 lines from the connector to the MCU pads cleanly without manual intervention, but the geometric agent prioritized clearance around nearby passive components over pair symmetry. It split the differential pair around a test point cluster, running trace D+ on the top layer while shifting D- through two vias to Layer 3 before bringing it back up.

This introduced severe intra-pair skew (over 22 ps) and destroyed the differential impedance profile, causing impedance swings between 74 and 108 ohms. For low-speed UART or general-purpose GPIOs, this routing is fine. For USB High-Speed, it guarantees bit errors and failed eye-diagram compliance tests.

Quilter Results

Quilter maintained the differential pair constraint throughout the entire trace path. Using the integrated Simbeor field solver, it calculated the exact trace width and gap required for the specific prepreg dielectric constant ($\varepsilon_r = 4.1$ at 1 GHz) to achieve a flat 90-ohm differential impedance profile.

When navigating past component obstacles, Quilter routed both traces together on the top layer, maintaining equal distance and symmetrical bends. Length tuning meanders were inserted automatically near the source pins to eliminate skew, keeping the total intra-pair length delta below 0.2 mm. The impedance profile remained flat within 2.5% of nominal across the full line length.

Power Delivery Networks, Decoupling, and Switch Nodes

High-speed digital ICs draw transient currents with nanosecond rise times. Decoupling capacitors must supply this charge instantly, which means the parasitic loop inductance of the bypass capacitor mounting must be minimized. Similarly, switching regulators generate high-frequency magnetic fields proportional to the surface area of their high dI/dt hot loops.

POOR (Long dogbone traces add parasitic loop inductance):
[ IC Pin ] -------------- Traces (3mm) --------------> [ Cap Pad ]
                                                              |
                                                            (Via)

OPTIMAL (Via-adjacent routing minimizes inductance loop):
[ IC Pin ] === [ Cap Pad ] === (Via to Solid GND)

Bypass Capacitor Placement and Inductance

A standard mistake of basic autorouters is treating a bypass capacitor as an ordinary net connection that can be resolved anywhere on the net. DeepPCB often routed power traces from the main regulator rail through long dogbone traces, hitting the decoupling capacitor pad as a secondary branch rather than forcing the power current to flow through the capacitor pad before reaching the IC power pin.

Quilter enforces topological rules for bypass passives. It recognizes component associations from the schematic context, placing and routing bypass capacitors with minimum pin-to-pad distances. The power and ground vias are placed immediately adjacent to the capacitor pads, keeping total mounting loop inductance under 1.2 nH. The high-frequency transient current is forced through the capacitor, preserving the power integrity of the MCU rail under heavy digital switching loads.

Switching Converter Hot Loops

The buck converter stage in our test layout represents a major noise generator. The loop formed by the input capacitor, the high-side MOSFET, the low-side freewheeling diode (or synchronous FET), and ground carries discontinuous current pulses with di/dt values exceeding 2 A/ns.

DeepPCB: Routed the switch node (SW) as a wide track, but ran it across two layers using multiple standard vias, traversing directly above an analog sensor trace on Layer 3. The large surface area and high via count created strong capacitive coupling between the noisy SW node and the high-impedance analog trace, injecting 180 mV of switching noise into the ADC input during simulation.
Quilter: Restricted the switch node to a compact polygon on the top layer directly between the regulator output pin and the power inductor. It maintained an unbroken ground plane on Layer 2 underneath the entire switching stage and pushed all sensitive analog routing outside the magnetic perimeter of the power stage.

Where DeepPCB Outperforms Quilter

Physics solvers carry real computational overhead. While Quilter delivers superior signal integrity and EMC compliance on sensitive boards, DeepPCB holds distinct advantages in specific operational contexts.

                    AUTOROUTER SELECTION MATRIX

           Low / Medium                       High / Critical
        +-------------------------------+-------------------------------+
        |                               |                               |
   H    |       DEEPPCB SWEET SPOT      |      QUILTER SWEET SPOT       |
   i    |                               |                               |
   g    | - Dense digital backplanes    | - Mixed-signal HDI boards     |
   h    | - LED driver / matrix arrays  | - RF / High-speed USB / PCIe  |
        | - Non-critical microcontroller| - Switch-mode power stages    |
   D    |   breakouts                   | - Precision analog front-ends |
   e    |                               |                               |
   n    +-------------------------------+-------------------------------+
   s    |                               |                               |
   i    |       CONVENTIONAL ROUTING    |      MANUAL CRITICAL ROUTE    |
   t    |                               |                               |
   y    | - Simple 2-layer breakouts    | - RF front ends & antennas    |
        | - Low-speed breakout boards   | - Extreme low-noise analog    |
   L    | - Basic Arduino / sensor shields| - Isolated power topologies |
   o    |                               |                               |
   w    +-------------------------------+-------------------------------+

1. Raw Completion Rate on Pure Digital Topologies

On large, purely digital designs with thousands of non-critical nets (such as large LED display driver matrices, test fixtures, or complex pin-to-header breakout boards), DeepPCB routes faster and achieves higher completion rates. DeepPCB routinely finishes 100% of connections on complex 4-layer and 6-layer digital boards where physics-first engines fail to complete the last 3% of nets due to over-constraining rules. DeepPCB completed its first candidate solution in roughly one-tenth the compute time required by Quilter's full multi-physics pass.

2. Via Minimization in Non-Critical Layouts

Because DeepPCB's reinforcement learning agent is directly rewarded for minimizing via counts, it excels at finding clever topological escape paths across available routing channels. On open-source reference boards, DeepPCB frequently produces routes using up to 40% fewer vias than conventional autorouters, cutting parasitic via capacitance and improving drill cycle times during board fabrication.

The Mixed-Signal Decision Framework

If you are an engineer shipping hardware on a tight budget, choosing between pure RL autorouting, physics-driven layout, and manual routing comes down to your board's frequency domain, layer count, and noise tolerance.

Scenario A: Pure Digital / Low-Frequency Control Boards

Examples: Motor controller interfaces, smart home sensor breakout boards, lighting control matrices, low-speed microcontroller boards (operating below 25 MHz without high-speed interfaces).
Recommended Tool: DeepPCB.
Why: You need routing throughput. Signal integrity risks are negligible because trace lengths are much shorter than signal wavelengths. DeepPCB will complete the routing in minutes, minimize drill operations, and save you hours of manual layout.

Scenario B: High-Density Mixed-Signal & High-Speed Edge Compute

Examples: Sensor fusion boards with 24-bit ADCs, embedded Linux systems with DDR3/DDR4 memory, boards with USB 2.0/3.0, PCIe, or Ethernet interfaces, compact DC-DC converters.
Recommended Tool: Quilter (or automated hybrid platforms like IntelCAD that integrate circuit constraint validation).
Why: You cannot compromise on return path geometry or power loop parasitics. A layout that passes connectivity DRC but fails physics checks will cause mysterious system crashes, ADC noise floor degradation, and EMC compliance failures at the test lab.

Scenario C: High-Power RF and Precision Analog

Examples: Sub-gigahertz RF front-ends, 5.8 GHz transceivers, ultra-low-noise transimpedance amplifiers for optical receivers.
Recommended Tool: Manual layout for critical paths, followed by automated tools for peripheral digital buses.
Why: No current AI autorouter fully replaces the nuanced electromagnetic modeling needed for distributed matching networks, microstrip filter layouts, and precise co-planar waveguide ground stitching. Hand-route the sensitive RF core and analog inputs first, lock those tracks, and hand off the remaining digital lines to an automated engine.

Practical Rules for Using Automated Routers Today

If you plan to run automated routing tools on your next production revision, follow this practical checklist to keep your boards clean:

Define Hard Keepout Zones for Split Planes: Never let an autorouter choose where to transition reference layers. Define explicit keepouts on all internal signal layers over split planes before starting the autorouting engine.
Manually Place and Lock Switching Nodes: Place your buck/boost inductors, input bypass capacitors, and catch diodes by hand. Draw a tight copper pour for the SW node and lock it. Let the automated tool route everything else.
Specify Exact Impedance Profiles in Schematic Metadata: Do not rely on geometric trace width defaults. Ensure your tool imports layer stackup parameters, copper thickness, and dielectric constants directly so that impedance-aware solvers like Simbeor can calculate true microstrip dimensions.
Run Post-Route Return Current Audits: After the autorouter completes the board, inspect your ground reference planes on Layers 2 and 5. Look for lines of vias that form virtual slots in the copper plane. If you find unbroken lines of vias, space them manually to restore continuous ground return paths.

Automated PCB layout tools have finally moved past the primitive grid-based autorouters of the past twenty years. Understanding whether an engine optimizes for topological completion or electromagnetic physics allows you to harness their speed without getting burned by failed EMC scans on your first production batch.