Keysight and WIN Semi Automate 3D EM Verification for GaN MMICs

Keysight and WIN Semiconductors have integrated 3D EM and multi-domain simulation into a single PDK workflow, eliminating manual layout extraction loops for GaN and GaAs MMICs.

Keysight Technologies and WIN Semiconductors have released an automated design and verification workflow that couples non-linear circuit simulation, 3D electromagnetic (EM) layout modeling, and off-chip evaluation board design into a single environment. The target is high-frequency compound semiconductor design: gallium arsenide (GaAs) and gallium nitride (GaN) monolithic microwave integrated circuits (MMICs) operating across microwave and millimeter-wave bands for satellite communications, 5G/6G infrastructure, and phased-array radar.

In digital ASIC design, static timing analysis and automated place-and-route rely on well-defined abstraction boundaries. Standard cell timing is characterized into Liberty files, and parasitic extraction tools (such as StarRC or Quantus) generate lumped RC or distributed RLCK networks for sign-off.

MMIC design has never enjoyed that clean separation. At 28 GHz, 39 GHz, or 94 GHz, physical geometries do not merely carry parasitics; they are the circuit elements. Every microstrip bend, substrate via, and adjacent transmission line acts as a distributed resonator, transformer, or coupling mechanism.

When RF engineers transition from an optimized schematic to a physical layout in a compound semiconductor foundry PDK, circuit performance routinely falls apart. Center frequencies shift by 5 to 10 percent, amplifier stages become conditionally unstable, and output power drops. Fixing these discrepancies historically demanded manual, error-prone iterations between planar layout tools, separate 3D EM solvers, and circuit simulators. The Keysight and WIN Semiconductors integration attempts to close that loop.

The Extraction Bottleneck in Compound Semiconductor Fabs

Silicon CMOS and SiGe BiCMOS designers have long relied on DRC/LVS decks that extract parameterized passive components and parasitic interconnects. Compound semiconductor foundries like WIN Semiconductors operate under fundamentally different physical and mechanical constraints.

WIN Semi processes, including their 0.15-micron and 0.25-micron GaN-on-SiC (such as NP15 and NP25) and sub-micron GaAs pHEMT/HBT nodes, use thinned substrates (often 50 µm to 100 µm thick) with back-side metal grounding and through-wafer via holes (source vias). Passive networks consist of thick front-side gold metallization (airbridges, microstrip lines, interdigital capacitors, and metal-insulator-metal capacitors) fabricated over low-dielectric-constant passivation layers.

At low gigahertz frequencies, compact analytic models for microstrip tees, cross-junctions, and MIM capacitors match physical measurements reasonably well. But as frequencies push past 20 GHz, several secondary physical phenomena invalidate classical lumped or 2D analytic approximations:

Ground Via Inductance and Mutual Coupling: Through-substrate vias do not provide an ideal zero-ohm ground. A 50 µm deep via introduces roughly 15 pH to 30 pH of series inductance. When multiple active transistor fingers share a back-side via or when adjacent ground vias sit within close proximity, mutual inductive and capacitive coupling creates shared return currents. In a multistage GaN power amplifier, this shared ground path turns into an unexpected feedback loop, inducing odd-mode oscillations or severe gain ripple.
Proximity and Enclosure Effects: High-Q inductors, Lange couplers, and Wilkinson splitters tightly packed on a 2 mm by 2 mm die exchange fringing fields. Planar 2.5D Method of Moments (MoM) solvers can capture planar coupling on a single plane, but they struggle when currents travel vertically through airbridge posts, thick metal sidewalls, and deep via transitions.
Dielectric Discontinuities and Substrate Modes: Substrate thinning is mandatory to suppress surface-wave propagation and substrate modes. Yet at millimeter-wave frequencies, the transition from on-chip coplanar waveguide (CPW) or microstrip to bond pads generates localized radiating fields that couple into adjacent bias lines or the metallic package lid.

In standard engineering workflows, identifying these effects requires the designer to manually slice the layout, define dozens of coaxial or differential ports, export the geometry to a stand-alone 3D finite element method (FEM) tool, simulate the passive metal stack, export a massive multi-port Touchstone (S-parameter) matrix, and wire that matrix back into the non-linear circuit schematic.

This cycle is notoriously brittle. If an internal port reference plane is misplaced by 10 µm, phase errors corrupt the impedance seen by the transistor. If a layout geometry changes by two microns to meet DRC spacing rules, the entire EM setup must be manually redone.

Mechanics of the Joint Workflow

The joint workflow between Keysight (leveraging PathWave ADS, RFPro, and the Nexus Connect architecture) and WIN Semiconductors embeds the 3D EM analysis directly inside the schematic-layout cockpit, using validated PDK process stacks and automated port placement.

+-------------------------------------------------------------------------+
|                       Keysight ADS / RFPro Cockpit                      |
|                                                                         |
|  +------------------------+                 +------------------------+  |
|  | Non-Linear Schematic   |                 | Physical Layout        |  |
|  | (Angelov / ASM-GaN     |<===============>| (WIN Semi PDK: NP15,   |  |
|  | compact models)        |  Continuous     | NP25, GaAs pHEMT)      |  |
|  +-----------+------------+  Co-Simulation  +-----------+------------+  |
+--------------|------------------------------------------|---------------+
               |                                          |                
               v                                          v                
+------------------------------+          +-------------------------------+ 
| Non-Linear Harmonic Balance  |          | Automated EM Partitioning     | 
| & Transient Envelope Engines |<========>| (Direct FEM / Planar Mesh,    | 
| (Load-pull, stability, EVM)  |          | No manual port slicing)       | 
+------------------------------+          +---------------+---------------+ 
                                                          |                 
                                                          v                 
                                          +-------------------------------+ 
                                          | Multi-Domain Synthesis Engine | 
                                          | - On-chip 3D interconnects    | 
                                          | - Off-chip launch / wirebond  | 
                                          | - Evaluation board transition | 
                                          +-------------------------------+

Rather than treating electromagnetic analysis as a post-layout validation gate, the workflow treats EM extraction as an interactive design step. This is achieved through three specific technical mechanisms:

1. Automated Net-Based EM Partitioning

Instead of requiring the designer to manually cut out polygons and assign boundary boxes, the environment parses the active and passive nets defined by the WIN Semi PDK. The tool recognizes active transistor cells (modeled by non-linear compact models like Angelov, EEHEMT, or ASM-GaN) and automatically treats them as circuit components, while routing the surrounding metallization, MIM caps, inductors, and substrate vias into the EM solver.

Ports are injected automatically at the exact physical boundaries of the active device terminals, with proper reference plane de-embedding. This avoids the common user error where parasitic feedlines are double-counted in both the active compact model and the passive EM field solution.

2. Multi-Domain Mesh Synthesis (Planar MoM and Full 3D FEM)

Compound semiconductor chips feature high aspect ratio metal structures. WIN Semi's thick metal options (such as 4 µm to 7 µm electroplated gold) mean that sidewall currents and conductor surface roughness (nodule formation at gold interfaces) have direct impacts on insertion loss at 40 GHz and above.

The integrated solver selects the appropriate numerical technique based on geometry. Planar structures with predominantly horizontal current flows are solved using accelerated Method of Moments. Vertical structures, through-wafer ground vias, airbridges, and wirebond transitions are handled by a 3D Finite Element Method engine without leaving the design database.

Because the tool shares the same underlying geometry engine as the layout editor, modifications in layout update the mesh parametrically. The designer does not re-export GDSII files or rebuild layer mapping tables.

3. Hierarchical EM-Circuit Co-Simulation

Once the EM solution converges, the tool automatically constructs a dynamic subcircuit back-annotated into the schematic. When running Harmonic Balance (HB) for power compression, X-parameters for non-linear behavioral modeling, or Circuit Envelope simulations for digital modulation (such as 5G NR FR2 waveforms or DVB-S2X carriers), the solver uses the full electromagnetic multi-port network directly.

This removes the traditional step of writing intermediate .sNp files to disk. It also avoids common Touchstone limitations, such as DC convergence failures caused by poorly extrapolated low-frequency points, or passivity and causality violations introduced by manual S-parameter truncation.

Handling Non-Linear Dynamics and High Power Density

GaN MMICs operate at extreme power densities, often ranging from 4 W/mm to 8 W/mm of gate periphery. Under these conditions, the interaction between layout parasitics and non-linear device operation cannot be analyzed using standard small-signal linear assumptions.

When a power amplifier is driven into deep gain compression (e.g., 3 dB to 6 dB into saturation), large-signal impedances shift dramatically across fundamental and harmonic frequencies ($2f_0, 3f_0$). An output matching network that looks perfectly matched under small-signal S-parameter conditions can present an inductive or capacitive mistune at the second harmonic under large-signal drive, destroying power-added efficiency (PAE) and driving channel temperatures up.

Parameter	Standard Fragmented Flow	Keysight-WIN Semi Automated Flow
Port Assignment	Manual polygon slicing and reference plane definition per port	Automatic net-based port assignment at active device terminals
EM Engine Setup	External GDSII export, manual layer mapping, manual port setup	Embedded MoM/FEM selection within PDK environment
Re-simulation Loop	Hours to days: re-export, re-mesh, re-wire S-parameter block	Minutes: direct parameter update and back-annotated co-simulation
Thermal & Active Coupling	Decoupled; thermal checked separately from RF layout	Integrated multi-domain (EM, non-linear RF, package parasitics)
Board-Level Transition	Isolated chip simulation; board transitions modeled as ideal 50Ω	Complete path: chip pad + wirebond / flip-chip + PCB launch
Risk Profile	High probability of first-pass frequency shift (3% to 8%)	High first-pass yield on center frequency, stability, and PAE

In high-power GaN layouts, thermal dissipation is closely coupled with electrical performance. High operating channel temperatures ($T_j > 175^\circ\text{C}$) reduce electron mobility in the 2DEG (two-dimensional electron gas) channel, degrading transconductance ($g_m$) and saturated drain current ($I_{dss}$).

By integrating WIN Semi's non-linear electrical models with 3D EM extraction, designers can perform harmonic load-pull contours directly on the layout geometry. If a drain manifold or matching stub causes impedance mistuning at $2f_0$, the engineer can resize the stub in the layout and immediately see the updated load-pull contours and PAE degradation in Harmonic Balance, without breaking the simulation hierarchy.

The Off-Chip Transition: Modeling the Evaluation Board

A critical addition in this workflow is extending the simulation boundary past the on-chip bond pad to include the off-chip MMIC evaluation board.

A substantial percentage of MMIC prototype failures do not occur on the gallium nitride die itself. They occur at the interface between the die and the test fixture or system package. Consider an X-band or Ku-band MMIC wire-bonded to a high-frequency laminate (such as Rogers RO4350B or RT/duroid 5880):

A standard 1-mil (25 µm) diameter gold bondwire presents roughly 0.8 nH to 1 nH of inductance per millimeter of length.
At 30 GHz, a 0.5 mm bondwire contributes approximately $j150,\Omega$ of series reactance.
Mutual inductive coupling between parallel bondwires (e.g., adjacent RF input and DC gate bias lines) creates sneak paths that degrade isolation and cause high-frequency instabilities.

The joint workflow allows designers to export the die layout into an evaluation board design environment where bondwires, ribbon bonds, flip-chip solder bumps, package cavities, and PCB launch transitions (e.g., grounded coplanar waveguide to microstrip steps) are co-simulated within the same 3D EM engine.

This end-to-end extraction ensures that the matching network designed on-chip explicitly accounts for the reactive loading of the packaging interface. Rather than attempting to compensate for bondwire inductance after fabrication through external PCB tuning stubs, the on-chip matching network absorbs the interconnect parasitics directly into the low-pass or band-pass filter structure of the MMIC.

Verification Realities: Stability and Out-of-Band Oscillation

Stability verification is where manual flows fail most expensive designs. A GaN HEMT has enormous gain at low frequencies (e.g., 1 GHz to 5 GHz), even when designed for an operational band of 28 GHz to 32 GHz. If the on-chip bias decoupling networks or off-chip board feeds present a negative resistance looking into the bias terminals at low frequencies, the amplifier will oscillate violently.

Traditional stability factor calculations ($K$-factor and $\mu$-factor) based on two-port S-parameters are insufficient for multi-stage, multi-finger power amplifiers. Two-port parameters treat the circuit as a black box; they cannot detect internal loop oscillations between parallel transistor cells or odd-mode oscillations across wide-gate peripheries.

To prove stability, designers must perform internal non-linear stability analysis (such as Nyquist analysis or driving-point impedance checks via auxiliary state variable probes) at every transistor terminal across the layout.

When passive layout elements are captured via an automated multi-port EM extraction, all internal node connections remain accessible to the circuit simulator. The designer can run stability checks across DC to 100 GHz at every gate and drain terminal while accounting for the full electromagnetic coupling of the supply rails and ground mesh. If an odd-mode oscillation is identified, the exact physical layout branch responsible for the parasitic resonance can be diagnosed and damped with on-chip resistors or layout modifications immediately.

EDA Automation Across Disciplines

As mixed-signal systems grow denser, the boundary between RF analog layout and automated digital design continues to blur. In advanced systems-on-chip and phased-array beamforming front-ends, high-speed digital control interfaces, digital pre-distortion (DPD) calibration paths, and non-linear RF power stages operate inches or millimeters apart.

While digital design teams rely on automated synthesis, formal verification, and strict RTL-to-GDS pipelines (where tools like Silicode automate digital front-end architecture and RTL generation), analog and RF teams remain bound to physical physics solvers. The Keysight and WIN Semiconductors collaboration demonstrates that automation in the RF domain does not mean abstracting away the physics as digital synthesis does. Instead, it means automating the setup, execution, and back-annotation of physics solvers so that electromagnetic accuracy is maintained without slowing down iteration cycles.

By reducing the friction of full 3D EM extraction, compound semiconductor design can approach the first-pass predictability long demanded by high-volume digital workflows.

Practical Recommendations for Design Audits

For engineering teams preparing for tapeout on WIN Semiconductors GaAs or GaN nodes using Keysight ADS and RFPro, several layout and simulation practices should be standardized across the design review:

Do Not Trust Pure Planar EM for Back-Side Vias: Ensure all ground transitions, through-wafer vias, and multi-layer ground returns are computed using 3D FEM or planar solvers validated with vertical conductor support. Do not approximate substrate vias as simple series inductors in millimeter-wave bands.
Run Large-Signal Stability Across All Nodes: Never sign off on a design based purely on two-port small-signal $K$-factor analysis. Perform non-linear loop gain or Nyquist stability analysis on every active cell, incorporating the full EM multi-port S-parameter matrix of the passive layout.
Include the Packaging Transition in Sign-Off: Simulate the complete launch interface, including bondwire length tolerances ($\pm 20%$ variations in loop height and lateral displacement), PCB substrate dielectric tolerances, and enclosure cavity modes. An amplifier unconditionally stable on-chip can easily oscillate inside a metallic package due to lid-induced cavity resonance.
Verify Conductor Sidewalls and Surface Roughness Models: Ensure the PDK EM stack configuration accounts for metal thickness sidewall profiles and surface roughness parameters matching WIN Semi's specific gold deposition process. Neglecting these can cause an underestimation of insertion loss by 0.2 dB to 0.5 dB per stage, significantly reducing overall PAE in multi-stage power amplifiers.
Audit Port Placement Boundaries: In automated EM extractions, verify that port reference planes lie exactly at the boundary of the compact device model keep-out zone to prevent double-counting of terminal metal parasitics.

Compound semiconductor fab runs remain expensive, with typical GaN mask sets and dedicated prototype wafer runs running between $80,000 and $250,000 with cycle times stretching from 14 to 26 weeks. Workflows that tightly bind 3D EM solvers, foundry PDK rules, and non-linear active simulation are the only practical defense against multi-month respin delays.