A four-layer board can pass every design rule check in KiCad or Altium, report zero unrouted nets, show zero clearance violations, and still fail within five seconds of powering up on your bench.
The microcontroller resets every time the 12V-to-3.3V buck converter steps into continuous conduction mode. The 12-bit ADC reads two dozen counts of noise on what should be a quiet sensor rail. The SPI bus drops packets at 10 MHz despite looking pristine on the schematic. When you put a near-field probe over the board, the ground plane glows like an antenna.
This is the wall automated routing keeps running into. Tools powered by reinforcement learning, including DeepPCB and early iterations of Quilter, promise to eliminate the manual grind of track laying. DeepPCB reports over 100,000 processed boards and 18,000 users. Quilter and newer startups are throwing compute at full-board layout synthesis. Marketing pages show complex rat nests dissolving into smooth traces in minutes.
Yet on the benches of solo hardware engineers, startup leads, and hardware consultancies, these layouts routinely get ripped up. The software solved a topological maze, but it ignored the electromagnetic fields travelling through the dielectric.
To understand why full-board autonomous routing still generates costly fab respins, you have to look at what autorouters actually optimize for, how mixed-signal return paths work in the real world, and why topological completion is only half the battle.
The DRC Clean Illusion
Traditional autorouters from the 1990s and 2000s, like the Specctra router or the legacy engines baked into Altium and OrCAD, treated PCB layout as a strict grid-based maze. The goal was simple: connect point A to point B without crossing tracks, violating track-to-track clearances, or exceeding maximum via counts. If the netlist completed with zero DRC errors, the software considered its job done.
Modern reinforcement learning tools replace hardcoded heuristics with neural networks trained on reward functions. The agent receives positive reinforcement for completing nets and negative reinforcement for via count, trace length, and clearance violations. It explores thousands of layout variations, learns geometric strategies like escape routing from fine-pitch packages, and outputs a complete board in minutes.
The fundamental flaw has not changed: clearance rules are geometrical, but signal integrity is electromagnetic.
A design rule checker only checks if copper touches copper where it should not. It does not know that routing a 3.3V digital trace across a split in layer 2 turns that trace into a slot antenna. It does not calculate the mutual inductance between an inductor switch-node copper pour and a high-impedance feedback trace running parallel on the next layer. It cannot tell you that three decoupling capacitors placed 8 mm away from an STM32 VDD pin might as well not be on the board at all.
When an AI autorouter declares a layout 100% routed and DRC-clean, it has satisfied the fabricator's manufacturing minimums, not the laws of electrodynamics.
The Return Path Problem in 2-Layer and 4-Layer Boards
Most high-volume consumer and industrial electronics run on tight BOM constraints. You do not get an eight-layer board with dedicated, unbroken ground planes for every signal layer. You get a cheap 2-layer FR4 stackup or a standard 4-layer JLC7628 stackup (Signal-Ground-Power-Signal, with a thick 0.8 mm to 1.0 mm core between inner layers).
In these stackups, return paths matter far more than forward paths.
4-Layer Standard Stackup (JLC7628 / 1.6mm total thickness)
Layer 1 (Top Signal / Power): 0.035 mm copper (traces, components)
Dielectric 1 (Prepreg 7628): 0.210 mm (FR4, Er ~ 4.5)
Layer 2 (Internal Plane): 0.017 mm copper (Ground Reference)
Dielectric 2 (Core): 1.065 mm (FR4, high loop inductance to L4)
Layer 3 (Internal Plane): 0.017 mm copper (Power or Ground Split)
Dielectric 3 (Prepreg 7628): 0.210 mm (FR4, Er ~ 4.5)
Layer 4 (Bottom Signal): 0.035 mm copper (low-speed routing)
When a signal transitions from high to low at a fast slew rate (say, 1.5 ns on a modern 3.3V CMOS output), the return current does not travel through the path of least resistance. It travels through the path of least impedance, which is the path of least inductance. That means the return current hugs the ground plane directly underneath the signal trace to minimize the loop area $A$.
The magnetic loop inductance of a current path is directly proportional to this loop area:
$$L_{loop} \approx \mu_0 \cdot \frac{h \cdot l}{w}$$
Where:
- $h$ is the dielectric height between the trace and the reference plane
- $l$ is the length of the trace
- $w$ is the width of the trace
When an automated router needs to get five tracks across a 2-layer board, it drops vias and runs those tracks across the bottom layer. In doing so, it slices the bottom ground pour into isolated islands. The return current for high-speed signals must now detour around these slots, blowing open the loop area by a factor of ten or twenty.
The result is immediate:
- The radiated emissions jump by $20\log_{10}(\Delta A)$ dB, failing regional EMC compliance tests (CISPR 32 / FCC Part 15).
- Ground bounce ($V = L \frac{di}{dt}$) spikes during simultaneous switching outputs, corrupting nearby analog signals.
- Crosstalk between adjacent traces increases because the electromagnetic fields spread outward instead of remaining tightly bound to the reference plane.
In video testing run by Dave Jones on EEVblog (EEVblog 1535), DeepPCB was tested on a simple double-sided board. The tool repeatedly sliced up the continuous ground plane, snaked tracks across both sides arbitrarily, and dropped ground vias in locations that choked current return paths. The software saw empty board area as free routing real estate. A human layout engineer sees empty ground plane as a sacred shield that must never be broken without an immediate stitching bridge.
Parasitics and Switching Regulators
Every hardware team building IoT nodes, industrial controllers, or motor drivers includes at least one switch-mode DC-DC converter on the board. Consider a standard buck regulator like the Texas Instruments TPS54302 stepping 24V down to 3.3V at 3A with a 400 kHz switching frequency.
The switching node (SW) moves between 24V and ground in roughly 5 ns. The input current loop (from the input capacitor $C_{IN}$, through the high-side MOSFET, down to ground, and back into $C_{IN}$) experiences an instantaneous current step of several amperes:
$$\frac{di}{dt} = \frac{3\text{ A}}{5\text{ ns}} = 6 \times 10^8\text{ A/s}$$
If the trace between the input capacitor and the IC pin contains just 2 nH of parasitic inductance (roughly 2 mm of standard trace and a standard 0.3 mm via), the induced voltage spike across that parasitic inductor is:
$$V_{spike} = L \cdot \frac{di}{dt} = (2 \times 10^{-9}\text{ H}) \cdot (6 \times 10^8\text{ A/s}) = 1.2\text{ V}$$
That 1.2V spike rides directly on top of the input rail. It stresses the internal FETs, causes switch-node ringing, and injects broadband noise straight into the board's power distribution network.
An experienced engineer places $C_{IN}$ directly against the VIN and GND pins of the regulator, uses wide copper polygons rather than traces, and avoids vias entirely in the high-frequency $di/dt$ loop.
What does a reinforcement-learning router do? It looks at the netlist. The netlist says VIN connects to pin 2 and $C_{IN}$. If the agent finds it geometrically convenient to place a via, route the net on layer 4 for 6 mm, and via back up to pin 2, it does so. The netlist is satisfied. DRC passes. But when you power the board up on the bench, the regulator oscillates, overheats, and burns out under a 1.5A load.
| Design Metric | Human Best Practice | Typical RL Autorouter Output | Bench Consequence |
|---|---|---|---|
| Buck $C_{IN}$ Loop | < 15 $\text{mm}^2$ loop area, same layer, direct polygon | Routed with tracks and 2+ vias | High $V_{spike}$, severe switch-node ringing, EMI fail |
| MCU Decoupling | Cap placed < 1.5 mm from VDD, pin routed through cap pad | Cap placed 5-10 mm away, connected by thin trace | High-frequency rail collapse during clock edges |
| Ground Continuity | Solid, unbroken polygon on Layer 2 | Sliced into strips by transverse signal traces | Ground bounce, slot radiation, ADC noise floor degradation |
| Via Count on Signal Nets | Minimal (0-1 via for simple escape) | 4-8 vias per net as solver escapes local minima | Uncontrolled via stub capacitance (~0.5 pF) and inductance (~1 nH) |
| Analog Separation | Strict physical isolation of analog and digital returns | Interleaved analog and digital routing | Digital switching hash injected into sensitive op-amp inputs |
Placement Is 80% of Routing
There is an old rule in hardware design: if a board is hard to route, the placement is wrong.
When a human engineer places components, they are mentally routing the board at the same time. They orient ICs so that pin multiplexing aligns with peripheral connectors. They place crystal oscillators within 2 mm of the MCU pins with a dedicated ground island underneath. They place current sense resistors right at the bridge outputs with symmetrical Kelvin connections.
If you hand an AI autorouter a board where the components were placed without deep regard for current loops and signal flow, you are asking it to solve a mathematically impossible optimization problem. The router has to twist traces, drop vias, and lengthen paths just to find connectivity.
Quilter has highlighted this exact challenge in their technical engineering notes. If the optimization target is pure completion rate, the model inherits bad human placement and generates an unmaintainable maze to reach 100%. If an autorouter leaves 3% of the nets unrouted, those remaining nets are almost always the most critical, difficult signals on the board (like differential USB pairs or tight analog feedback loops) that were boxed into a corner by the automated tool.
Solving routing without co-optimizing component placement and physical stackup modeling is attempting to solve the symptom rather than the cause.
Decoupling Layout Comparison
Optimal Human Layout (Low Inductance):
[ Power Rail ] ---> [ Cap Pad ] ---> [ IC VDD Pin ]
| |
[ Ground Via ] [ Ground Via ]
Naive Autorouter Output (High Parasitic Inductance):
[ Power Rail ] --------+--------> [ IC VDD Pin ]
|
(6mm Trace)
|
[ Cap Pad ]
|
(3mm Trace)
|
(Layer 4 Via) ---> (Ground Return)
In the naive layout on the bottom, the trace length and extra via add 3 to 5 nH of parasitic inductance in series with the capacitor. At 100 MHz, 4 nH of inductance presents $j\omega L = j(2\pi \cdot 10^8 \cdot 4 \times 10^{-9}) \approx +j2.51,\Omega$ of inductive reactance, completely destroying the capacitor's ability to shunt high-frequency switching transients to ground.
Why Real-Time Physics Solvers Are Hard to Build
Why haven't AI teams simply added Maxwell's equations to the reinforcement learning reward function?
Because finite-element electromagnetic field solvers are computationally brutal. Running a full 3D or 2.5D field simulation (like Ansys HFSS or Cadence Clarity) on a moderately complex board can take anywhere from fifteen minutes to four hours on a dedicated 64-core workstation.
A reinforcement learning model needs to evaluate millions of states during training and thousands of candidate iterations during an inference pass. If every step requires solving Maxwell's equations to verify return path inductance and loop areas, the layout process would take weeks of compute time per board.
Instead, RL engines rely on mathematical approximations: bounding boxes, Euclidean distance penalties, Manhattan routing costs, and clearance grids. These heuristics run in microseconds, but they discard the phase, frequency, and return path dynamics of real electronics.
Neural networks excel at pattern recognition within well-defined data distributions. But as DeepPCB noted in their engineering retrospectives on the 60-year routing problem, PCBs do not form a clean, coherent mathematical distribution.
A layout for a 1 kW BLDC motor driver has almost zero design overlap with a 2.4 GHz BLE sensor beacon, which has zero overlap with an 8-layer industrial compute module with DDR4 memory. Training a model on 100,000 open-source GitHub boards often means training it on amateur designs, unvalidated hobbyist schematics, and flawed layouts that happened to pass DRC.
What Actually Works on the Bench Today
Autonomous, full-board push-button routing is not ready to replace a skilled hardware engineer on mixed-signal hardware. But dismissing all automation is a mistake. Modern engineering teams are finding high leverage by applying automation to narrow, well-bounded sub-problems.
Here is where automation actually saves design time without risking a $1,500 fab respin:
1. Interactive Push-and-Shove Engines
The interactive push-and-shove routers in modern EDA tools (pioneered by Specctra, refined in Altium, and executed cleanly in KiCad's modern router) remain the gold standard for daily productivity. The human engineer decides the topology, reference plane, and layer transitions. The tool handles the micro-clearances, shoving adjacent traces and sliding vias dynamically without violating constraints.
2. Length Tuning and Delay Matching
Routing high-speed memory buses (like DDR3/4) or differential pairs (USB, Ethernet, CAN-FD) requires precise trace length matching to prevent skew. Doing this manually with serpentine traces is tedious. Modern length-tuning engines calculate propagation delay based on layer dielectric properties and inject meanders automatically. This is pure geometric math with clear physical boundaries, making it ideal for automation.
3. Escape Fanouts on Dense Packages
Breaking out 0.5 mm or 0.8 mm pitch BGAs and 100-pin QFPs consumes hours of setup. Fanout automation tools drop uniform diagonal vias, set dog-bone patterns, and route traces cleanly out to the perimeter where the engineer can take over. The boundary conditions are tight, predictable, and save pure mechanical drafting time.
4. Deterministic Power Plane Generation
Tools that calculate DC current density and drop copper pours with thermal relief based on current carrying requirements (IPC-2152 standards) remove manual calculation errors. They highlight current bottlenecks and excessive via heating before sending Gerbers to the fab.
At IntelCAD (intelcad.ai), this pragmatic boundary is the core focus: rather than treating PCB layout as a black-box video game for an AI agent to solve arbitrarily, automated layout tools must combine constraint-driven synthesis with strict reference plane awareness and deterministic verification.
The Real Cost of a Respin
For an early-stage hardware startup or a lean engineering team, tool subscription costs are trivial compared to the cost of a blown schedule.
Consider a typical 4-layer prototype cycle through an agile fab:
- Bare PCB fabrication (5-day standard turn at JLCPCB or PCBWay): $120
- Component procurement (DigiKey / Mouser BOM for 5 boards): $450
- SMT assembly setup and stencils: $300
- Shipping and customs: $150
- Direct cash out per run: ~$1,020
Now add the real cost: engineering time.
When the prototype arrives with intermittent sensor resets caused by broken return paths, you spend three days in the lab with an oscilloscope, a current probe, and copper foil trying to isolate the problem. You identify the bad layout, modify the copper, update the design, and order Revision B.
You have burned $1,020 in direct costs, $3,500 in engineering time, and two full weeks of market lead time. If Revision B has another grounding issue because an autonomous tool routed the analog reference through a digital switching plane, the product launch slips by another month.
Cost of a Single PCB Respin Cycle
----------------------------------------------------
Direct Fab & Assembly Costs: $1,020
Bench Debugging (24 hrs @ $150/hr): $3,600
Respin Layout & Verification (12 hrs): $1,800
Schedule Delay Impact (2 weeks): Priceless
----------------------------------------------------
Total Cost per Unnecessary Respin: $6,420+
Until an automated tool can understand high-frequency field paths, parasitic inductances, and component placement physics as well as it understands geometric clearances, push-button full-board routing remains a massive reliability risk for commercial mixed-signal hardware.
Practical Rules for Mixed-Signal Layout Today
If you want to speed up your PCB workflow without paying the respin penalty, use a disciplined hybrid approach:
- Lock Your Power and Decoupling Loops First: Manually place and route your switching regulators, input capacitors, inductors, and MCU decoupling caps. Use direct, wide copper pours on the component layer. Place your ground vias right at the capacitor pads. Once this is done, lock those footprints and traces in place.
- Preserve Your Primary Reference Plane: On a 4-layer board, keep Layer 2 as an unbroken, continuous ground pour. Do not allow any tool (human or automated) to route signal tracks on Layer 2. If an escape requires dropping to an inner layer, drop to Layer 3 or Layer 4, and drop an adjacent ground via if crossing between different reference planes.
- Use Automation for Non-Critical Net Routing: Once power paths, analog front-ends, high-speed clocks, and differential pairs are manually locked down, let autorouting or interactive tools handle the mundane 3.3V digital GPIOs, LED indicators, and slow configuration nets.
- Audit Return Paths with a 2D Eye: Turn off all layers in your EDA tool except the signal layer and its immediate ground reference plane. Trace each high-speed signal from driver to receiver, and visually verify that there is a continuous strip of copper directly beneath it for the entire run.
Automation in electronics design is accelerating rapidly, but physics does not yield to statistical models. The engineers who ship reliable hardware on time are not the ones who hand everything over to a black-box router. They are the ones who let software handle the repetitive drafting while keeping absolute control over the current loops, the ground planes, and the laws of electromagnetism.
Sources
- DeepPCB: deeppcb.ai
- Quilter Technical Blog: Why New Routing Problems Keep Breaking Old Tools
- DeepPCB Engineering: The 60-Year Routing Problem Nobody Solved
- EEVblog: EEVblog 1535 - DeepPCB AI AutoRouting TESTED!
- Altium: The Altium PCB Auto Router
- Quilter: A 2026 Guide to Automated PCB Routing