Every hardware engineer knows the feeling of running an automated routing tool, watching the completion counter hit 100%, and then turning off the top copper layer to see that the ground plane underneath looks like a block of Swiss cheese.
The tool reported zero Design Rule Check (DRC) violations. Trace widths matched net classes. Clearances met the 5-mil fab minimums. But the board will fail emissions testing at the lab or reset every time a nearby relay clicks, because the algorithm has no inherent understanding of return path loop inductance.
Over the past two years, automated PCB design has shifted away from classic 1960s Lee-Moore maze routers and basic rip-up-and-retry heuristics toward machine learning. The two cloud-based platforms generating the most interest among small hardware teams are DeepPCB (built on reinforcement learning models developed at InstaDeep) and Quilter (which uses a physics-driven layout compiler paired with reinforcement learning).
DeepPCB claims median routing times under five minutes and 95%+ completion rates across tens of thousands of KiCad boards. Quilter advertises autonomous placement and routing from raw schematics exported out of Altium, Cadence, or KiCad.
If you are the sole electronics engineer at a hardware startup, the promise is seductive. Board layout takes 30% to 50% of your development cycle on a new revision. Cutting that down to an afternoon run would save thousands of dollars in engineering hours and speed up your spin cycle. But when you look past the completion percentage, what do these engines actually do to your power delivery network, your high-speed signal integrity, and the physical copper you send to Eurocircuits or JLCPCB?
The Fundamental Divide: Geometric RL vs Physics Compilers
To understand why AI autorouters make specific layout mistakes, you have to look at what their neural networks are actually optimizing.
DeepPCB treats layout primarily as a constrained geometric search problem. You provide an existing placement, a netlist, and keepout boundaries. The reinforcement learning agent operates like a pathfinding algorithm trained over thousands of historical board layouts. Its reward function rewards completed connections, penalizes track length, penalizes via count, and strictly enforces geometric design rules (clearance, minimum trace width, board edge margins).
Because DeepPCB interfaces directly with KiCad via a plugin, it operates on the physical board file. It does not inspect your schematic hierarchy or your component data sheets. It sees a graph of pins that must be connected by copper tracks without intersecting each other or crossing board boundaries.
Quilter takes a fundamentally different route. Instead of taking a pre-placed board and solving the routing puzzle geometrically, Quilter ingests the schematic and the board outline. It attempts to compile the schematic into physical space using physics-driven constraints.
Because Quilter reads the schematic netlist directly, it can infer circuit topology: it recognizes that a 100 nF ceramic capacitor sitting between pin 4 of an IC and ground is a decoupling capacitor that belongs physically adjacent to that pin, not 15 millimeters away across the board. Quilter runs multiple candidate placements and routing passes in parallel on cloud instances, scoring each candidate against thermal, parasitic, and geometric models before presenting the best candidates to the engineer.
This architectural difference dictates how each tool handles the messy physical realities of mixed-signal hardware design.
The Ground Plane Tax: Return Paths and Hidden Slot Antennas
In standard 4-layer board designs (such as a standard SIG-GND-PWR-SIG stackup), Layer 2 is typically a continuous, unbroken ground reference plane. In theory, high-frequency return currents follow the path of least inductance, flowing directly underneath the signal trace on Layer 1.
When a human layout engineer routes a dense 4-layer board, they guard that Layer 2 ground plane fiercely. If a signal must jump to Layer 4, the engineer places a ground return via right next to the signal via to preserve the return path and keep the loop area near zero.
Reinforcement learning agents without continuous 3D field solvers do not think about return current loops unless explicitly penalized by a reward function.
In DeepPCB, the agent wants to clear the net. If routing five digital lines on Layer 1 requires dropping down to Layer 2 because Layer 1 is congested near a microcontroller, a geometric RL engine will happily drop vias and route copper tracks across Layer 2. If Layer 2 was defined as a filled copper zone, those tracks cut channels through the ground pour.
When ten signals do this simultaneously, Layer 2 becomes a comb of isolated copper islands. A high-speed SPI clock line running on Layer 1 across those cuts no longer has a continuous ground return underneath it. The return current must divert around the cut, creating a massive current loop. That loop acts as an efficient magnetic dipole antenna, radiating RF energy and picking up noise from nearby switching nodes.
Quilter mitigates this by maintaining explicit layer assignments and treating reference planes as structural constraints during its compiler pass. It attempts to keep primary reference planes intact and routes non-ground signals on dedicated routing layers. However, when board density climbs and board area shrinks, even a physics-driven compiler faces routing congestion.
If the component placement creates routing bottlenecks, the compiler is forced to make compromises. It may lengthen non-critical traces or drop vias into power planes to avoid cutting reference planes, which leads to another engineering issue: via clustering.
Decoupling Capacitors and Loop Inductance
Consider an STM32G4 microcontroller in an LQFP-64 package or a buck converter IC like the Texas Instruments TPS62840. The manufacturer data sheet specifies that each VDD/VSS pair requires a 100 nF 0402 ceramic bypass capacitor placed as close as possible to the pins, with vias placed to minimize parasitic loop inductance.
A standard rule of thumb is that every millimeter of trace adds roughly 1 nH of inductance, and a standard through-hole via adds 0.5 nH to 1.2 nH depending on the barrel height and diameter. If your decoupling loop has 5 nH of parasitic inductance, the capacitor cannot suppress 50 MHz switching transients.
Here is what happens when you feed this circuit to an automated router:
- Long Trace Stubs to Bypass Caps: DeepPCB sees that VDD on the IC and Pin 1 on the capacitor share a net. If the capacitor was placed 4 mm away during manual component layout, DeepPCB will route a thin 6-mil trace between them, then drop a via to the power plane somewhere in the middle. The decoupling loop area is massive.
- Via Placement on the Wrong Side of the Pad: A proper layout forces high-frequency current to flow from the IC pin, past the capacitor pads, and then down into the plane. Geometric routers frequently drop the via directly at the IC pin and run a secondary trace to the capacitor pad. The capacitor is now sitting on a stub, largely isolated from the high-frequency current path.
- Shared Ground Return Vias: To minimize total via count, an RL router will often tie the ground pads of three adjacent decoupling capacitors together with a short trace and use a single via to connect them all to Layer 2. That shared via introduces mutual inductance between the decoupling networks of different supply rails, coupling noise directly between domains.
Quilter handles this noticeably better when it performs both placement and routing, because its compiler clusters bypass capacitors with their parent IC power pins before laying down tracks. But if you import a pre-placed board into an AI router, the router is at the mercy of your component coordinates. If your placement is sub-optimal by even one millimeter, the router will find the shortest geometric path to close the net, regardless of loop parasitics.
High-Speed Differential Pairs and Phase Skew
Differential signaling (USB 2.0 High Speed at 480 Mbps, 100Base-TX Ethernet, or RS-485 transceiver lines) requires tight coupling, controlled impedance, and matched electrical lengths.
Most manual PCB designers dread routing differential pairs through tight spaces, making it a prime candidate for automation. But differential pairs break down under purely geometric routing:
| Routing Challenge | Human Layout Engineer | DeepPCB (KiCad Plugin) | Quilter (Physics Engine) | Freerouting (Classic Heuristic) |
|---|---|---|---|---|
| Intra-pair Skew | Manually adds phase bumps near the mismatch point | Treats traces as independent nets unless net-classed; often introduces length mismatch | Enforces length-matching constraints defined in schematic | Struggles with tight pair coupling; creates zigzag detours |
| Reference Plane Transitions | Drops ground stitching vias adjacent to signal vias | Drops signal vias without dedicated ground return paths | Attempts to maintain reference continuity; via pairing varies by density | Drops vias wherever clearance allows, ignoring return path |
| Obstacle Avoidance | Splits pair symmetrically around vias or pads | Splits pair unsymmetrically, causing sudden impedance spikes | Routes pair around obstacles while attempting to hold differential gap | Frequently breaks pair coupling completely to finish the net |
| Via Count per Net | Minimizes layer transitions (ideally zero or two) | Uses multiple layer hops (4 to 8 vias per net on dense areas) | Moderate via usage; clusters transitions | High via count with frequent doglegs |
When DeepPCB routes a board with differential signals, it treats the rules strictly as clearance and width constraints. If you define a differential pair in KiCad with 5-mil width and 5-mil spacing, DeepPCB will attempt to route the tracks in parallel.
However, when the pair hits a cluster of passives or an IC pin breakout, the algorithm will peel one trace away to navigate around an obstruction while sending the second trace along a different path, rejoining them a few millimeters later. That momentary split ruins differential impedance (shifting a nominal 90-ohm differential track to two isolated 50-ohm single-ended tracks) and introduces significant intra-pair skew.
Quilter handles differential pairs with significantly more discipline because you can declare differential pairs and skew tolerances in the schematic phase. The compiler will attempt to keep the traces locked together and generate serpentine delay lines to match phase.
Even so, when Quilter encounters a tight board edge or a dense pin-pitch connector, you will often find it introducing unnecessary meandering or taking wide detours around empty board space to satisfy length matching, consuming valuable routing channels needed by other nets.
The EEVblog Teardown: Why Via Count Explodes
A telling public demonstration of DeepPCB's underlying mechanics occurred during Dave Jones's EEVblog teardown (EEVblog #1535). Jones fed a simple double-sided microcontroller board into DeepPCB to see if reinforcement learning could beat a manual human layout or classic Freerouting.
The results highlighted the difference between mathematical optimization and human engineering judgment:
- DeepPCB Via Count: 77 vias on a simple 2-layer board.
- Freerouting Via Count: 49 vias on the exact same netlist and placement.
- Human Manual Layout: Less than 25 vias, with a completely intact bottom ground plane.
Why did the reinforcement learning model drop 77 vias on a board with only a few dozen components?
Because an RL agent operating under a time-budgeted search space discovers that hopping layers is an easy way to escape local minima. If a trace on the top layer is blocked by three existing tracks, routing around them might require a 20-step exploratory path with a high probability of colliding with other nets. Dropping a via to the bottom layer, moving 2 mm, and dropping another via back to the top layer solves the mathematical constraint in 4 steps.
To a computer, that is an efficient solution. To a manufacturing engineer, 77 vias on a 2-layer board means higher drill wear, potential reliability issues on cheap un-plugged HASL boards, and a bottom ground plane cut into so many ribbons that it ceases to function as a shielding layer.
DeepPCB has improved its algorithms since that early test, but the core tendency remains: geometric RL routers favor layer transitions over creative topological detours.
The "95% Complete" Illusion: The Cleanup Tax
DeepPCB frequently advertises that its median completion rate is 96.9%, with over 95% of boards hitting 95%+ completion in under five minutes.
For an engineering manager reading a marketing brochure, a 95% automated completion rate sounds like a 95% reduction in layout time. For the engineer who has to open the file and route the remaining 5%, it often means more work than routing the board from scratch.
Why? Because the AI autorouter routed the easiest 95% of the tracks using the best, most direct routing channels on the board. The remaining 5% of unconnected nets are disconnected precisely because the algorithm barricaded them behind a wall of traces and vias.
To connect the last five nets manually, you must do one of two things:
- Rip up 30% of the AI's completed traces to reopen routing corridors, effectively undoing the automated work.
- Add extra layer transitions, dropping traces down to internal planes, zig-zagging between vias, and making the board dirtier.
If you have ever inherited a mess of spaghetti routing from an intern, you know that cleaning up someone else's layout takes twice as long as starting with an empty board. The same rule applies to AI autorouters. If the tool cannot hit 100% completion while respecting physical constraints, the cleanup tax erodes most of the time you saved by not routing manually.
+-------------------------------------------------------------------------+
| THE ROUTING PARADOX |
| |
| Manual Routing: |
| [=== Critical Traces ===][==== Standard Buses ====][= GPIOs / Clean =]|
| 0% 40% 80% 100% |
| (Consistent, predictable progress; planes stay clean throughout) |
| |
| Pure Geometric AI Autorouting: |
| [================== AI Blitz Routing ==================][ Clean-up ] |
| 0% 95% 100% |
| (5 minutes to 95% completion... then 6 hours ripping up AI barricades)|
+-------------------------------------------------------------------------+
How to Actually Use AI Layout Tools Without Getting Burned
AI routing is not useless. It is simply immature when treated as a single-click black box.
If you want to use tools like DeepPCB or Quilter without causing a board respin, you must change your layout pipeline. You cannot treat them as drop-in replacements for an experienced layout engineer. You must use them as brute-force assistants for the low-risk, labor-intensive sections of your design.
1. Pre-route the Critical 20%
Never let an AI router touch your power delivery network, your switching regulator loops, your crystal oscillator lines, or your high-speed differential pairs.
Open your CAD tool (Altium, KiCad, or OrCAD) and manually route:
- The switching inductor, catch diodes, and input/output ceramic capacitors on all DC-DC converters.
- The crystal oscillator traces directly to the microcontroller pins, with an isolated ground guard ring.
- High-speed USB, Ethernet, MIPI, or SPI lines, keeping them strictly on Layer 1 over an unbroken Layer 2 ground plane.
- High-current power rails (make them wide copper pours, not thin traces).
Once those critical nets are routed, lock them in your CAD tool so the external engine cannot move, rip up, or nudge them.
2. Set Up Aggressive Keepout Zones
If you are using a 4-layer board and want Layer 2 to remain an unbroken ground plane, do not just hope the AI router will respect it. Go into your design rules and set a routing keepout on Layer 2 for all non-ground nets. Force the algorithm to route signal tracks on Layer 1 and Layer 4 only.
If the AI fails to route the remaining nets because it runs out of routing channels, that is an immediate signal that your board is too dense, your component placement needs work, or you need a 6-layer stackup. That is useful feedback. Letting the AI "solve" the congestion by cutting up your ground plane is not.
3. Use AI for Repetitive, Low-Speed Fanout
Where AI tools shine is fanout for low-speed peripherals: LED indicators, configuration pull-up resistors, GPIO headers, mechanical switches, and level shifters. Connecting 40 microcontroller pins to a 40-pin terminal block is tedious, brain-draining manual labor.
If your critical paths are locked and your ground layers are protected by keepouts, letting DeepPCB or Quilter chew on the remaining 80 non-critical nets while you grab a coffee is an effective use of automation.
4. Run Rigorous Post-Route Audits
When you pull the routed board back into your CAD editor, do not rely solely on the DRC check. Run a specific post-routing audit:
- Inspect the ground plane: Turn off all layers except Layer 2. Zoom in around your MCUs and dense ICs. Look for isolated ground islands, long slot cuts caused by via rows, and pins that have only a single narrow neck connecting them to the rest of the pour.
- Audit decoupling loops: Check every bypass capacitor. Verify that the trace goes from pad to plane via with minimum length, not through a wandering detour.
- Measure via counts: Compare the final via count against your manual baseline. If an automated run added 150 vias to a small board, trace where those vias are concentrated and eliminate unnecessary layer hops.
At IDO, our design workflows for IntelCAD focus heavily on keeping constraint definitions and physical verification front and center, ensuring that automated tools cannot bypass thermal, parasitic, and return path rules just to close a net.
What to Watch in Next-Generation Tools
The current generation of AI PCB tools is defined by a sharp divide: geometric reinforcement learning plugins operating inside desktop CAD on one side, and cloud-based physics compilers attempting full autonomous placement and routing on the other.
Over the next twelve months, watch whether tool developers integrate fast 2.5D electro-magnetic and parasitic solvers directly into the reinforcement learning inner loop. Right now, running a full field solver during an RL training run is computationally prohibitive, which is why engines use geometric proxies for signal integrity.
As surrogate neural network models for EM and thermal analysis improve, autorouters will begin optimizing for loop inductance, return path continuity, and radiated emissions in real time alongside basic trace clearances.
Until then, do not trust a 100% completion badge at face value. Protect your ground planes, lock your critical traces, and treat AI autorouters as fast drafting assistants rather than autonomous hardware engineers.
Sources
- [1] DeepPCB AI PCB Routing: https://deeppcb.ai/
- [2] Quilter 2026 Guide to Automated PCB Routing: https://www.quilter.ai/blog/a-2026-guide-to-automated-pcb-routing-traditional-autorouters-vs-ai-powered-layout
- [3] Protoflow AI PCB Autorouter Comparison: https://www.protoflow.ai/compare/ai-pcb-autorouter-comparison
- [4] Quilter vs DeepPCB vs Flux Guide: https://www.quilter.ai/blog/the-2026-guide-to-autonomous-pcb-design-quilter-vs-deeppcb-vs-flux-ai
- [5] EEVblog 1535 DeepPCB AI AutoRouting Test: https://www.eevblog.com/forum/blog/eevblog-1535-deeppcb-ai-autorouting-tested/
- [6] DeepPCB KiCad Plugin & Completion Benchmark: https://deeppcb.ai/kicad-autorouter-alternative/