Quilter vs DeepPCB on Real 4-Layer Hardware Constraints

We ran real mixed-signal 4-layer boards through Quilter and DeepPCB to see how physics solvers and RL handle return paths, impedance, and fab DRC.

If you hand a 4-layer mixed-signal board to an autorouter and send the raw Gerber files straight to JLCPCB or Eurocircuits, you will probably end up with a dead board or a compliance failure. That was true twenty years ago with Specctra, and it remains true today with modern AI-driven tools.

Yet the marketing around AI PCB design has shifted aggressively over the last two years. DeepPCB pitches reinforcement learning that routes boards in minutes via API. Quilter advertises physics-driven layout generation that places components and routes complete boards from a schematic netlist. Both promise to take trace-pushing off the plate of overworked hardware engineers.

For a solo engineer at a hardware startup, routing is often the single biggest time sink between schematic freeze and ordering prototypes. When you are managing the firmware, component sourcing, enclosure fit, and test fixtures alone, spending four days manually routing 400 nets on a dense 50 x 50 mm board feels like a bad use of time. If a tool can eliminate sixty percent of that work without introducing hidden signal integrity bugs, it is worth paying for. If it routes a 12-megahertz crystal line through a switch-node return path, it costs you two weeks and a thousand dollars in respins.

We ran both tools through practical 4-layer design problems to see what they actually produce. The test vehicle was a representative mixed-signal board: an STM32H7 microcontroller, high-speed USB 2.0 (480 Mbps), an external QSPI flash running at 80 MHz, a 24-bit analog frontend with a low-noise LDO, and a 2-amp synchronous buck converter stepping 12V down to 3.3V.

Here is how reinforcement learning and physics solvers actually handle the physical realities of modern boards.

The Test Stackup and the Problem of Return Paths

Most hardware startups build their first prototypes on standard 4-layer pool services. At JLCPCB, that is typically the JLC04161H-7628 stackup: 1 oz outer copper, 0.5 oz inner copper, with a thin 0.1 mm prepreg between Layer 1 and Layer 2, and a thick 1.2 mm core between Layer 2 and Layer 3. At Eurocircuits, the standard 4-layer stackup uses roughly 0.36 mm prepreg layers.

This geometry dictates your impedance and your return paths. On the thin-prepreg JLC stackup, a 50-ohm single-ended microstrip trace on Layer 1 needs to be roughly 7.5 mils (0.19 mm) wide over the solid ground plane on Layer 2. A 90-ohm differential pair for USB requires roughly 5.5 mil traces with 6 mil spacing.

The critical rule in mixed-signal 4-layer design is simple: high-frequency return currents travel directly underneath the signal trace on the adjacent reference plane. If a trace hops from Layer 1 to Layer 4, the return current must also hop from the Layer 2 ground plane to the Layer 3 power (or ground) plane. If you do not place a ground return via right next to that signal via, the return current takes a massive loop through the nearest decoupling capacitor or plane stitching via. That loop radiates EMI and picks up noise from whatever it wraps around.

How DeepPCB Handles It

DeepPCB runs on reinforcement learning models trained on vast corpuses of routing patterns. You bring your own component placement, define your keepouts and board outline, upload the board file or DSN, and let its cloud engine route the unrouted nets.

DeepPCB is remarkably fast at finding topological completion. It routes like a veteran game player trying to maximize an objective score: it finds paths through dense pin fields where older grid routers stall.

However, DeepPCB treats the board primarily as a 2D/3D connectivity graph. It understands clearance rules, trace widths, and net classes if you configure them properly. What it does not fundamentally understand is the high-frequency electromagnetic return loop.

When routing our 80 MHz QSPI lines (clock, CS, and 4 data lines), DeepPCB happily dropped vias on three of the six data lines to clear a cluster of pull-up resistors, while running the clock trace entirely on Layer 1. The three routed lines dropped to Layer 4, traversed under a cut in the Layer 2 ground plane caused by a cluster of thermal vias, and came back up to Layer 1 near the memory IC. There were zero adjacent ground stitching vias.

If you run this board, the phase skew and impedance discontinuities on the QSPI bus will cause intermittent read errors at 80 MHz, though it might boot fine if you drop the clock to 20 MHz in software. DeepPCB met every DRC clearance rule we gave it, but it failed the signal integrity requirements that were not explicitly encoded as geometric hard stops.

How Quilter Handles It

Quilter takes a different architectural approach. It does not just route; it attempts full autonomous layout. You provide the schematic, the netlist, the mechanical board outline, and the component models. Quilter's physics-driven compiler runs spatial optimization and thermal/EM simulations in the cloud, generating multiple layout candidates that you inspect and download.

Because Quilter integrates placement with routing, it clusters functional blocks more coherently than a purely topological autorouter. It placed the decoupling capacitors within 1.5 mm of the STM32 VDD pins and kept the QSPI flash directly adjacent to the MCU pins.

When Quilter routed the high-speed bus, it heavily penalized layer transitions on nets flagged for high speed. It kept the QSPI bus on Layer 1 against the uninterrupted Layer 2 ground plane. When it had to drop a signal to Layer 4, its solver placed an adjacent ground via within 25 mils of the signal via, provided the net rules specified a reference plane constraint.

The catch with Quilter is control. If you have tight mechanical constraints (for instance, an enclosure with specific connector locations, mounting boss clearances, and a display ribbon header), Quilter's placement engine can fight you. You have to specify every single mechanical keepout and locked position rigorously before you run the job. If your input constraints are sloppy, the output placement will look alien compared to conventional human layouts.

The Switching Regulator Test

The power section is where autorouters usually make their worst mistakes. We included a synchronous buck converter running at 2.2 MHz with an external inductor, input ceramic capacitors, and an output filter.

In a buck converter, the critical loop is the input loop: from the input capacitor, through the high-side MOSFET, through the low-side MOSFET to ground, and back into the negative terminal of the input capacitor. This loop contains high di/dt currents. If this loop area is large, the board will emit strong RF interference and create ground bounce that destabilizes your microcontroller.

Ideal Buck Layout:             Common Autorouter Mistake:

[ +12V In ]                    [ +12V In ]
     │                              │
  [C_IN] (Close!)                 [C_IN] ────── (Long trace) ────┐
     │                              │                            │
  [IC_VIN]                       [IC_VIN]                     [IC_SW]
     │                              │                            │
  [IC_SW] ── [Inductor] ── [VOUT]   [IC_GND] ── (Via to L2)   [Inductor]
     │                              │                            │
  [C_OUT]                        [C_OUT]                      [VOUT]
     │
 (Tight local GND return)

DeepPCB on Power Layout

Because DeepPCB requires you to place the components yourself, you can place the input capacitor right against the IC pins. However, when we ran the router without manually pre-routing the power nets, DeepPCB routed the input capacitor ground back to the main ground flood using a single 10-mil trace and two standard 0.3 mm vias, instead of a solid, low-impedance copper pour.

It also routed a sensitive analog feedback trace directly under the buck converter's switch node ($V_{SW}$) on the adjacent layer. The switch node swings 12 volts in roughly 4 nanoseconds. Placing a high-impedance feedback trace right below that copper node without a shielding plane injects massive capacitive switching noise directly into the regulator's error amplifier, causing output ripple and instability.

Quilter on Power Layout

Quilter's placement engine recognized the buck circuit topology from the schematic netlist and kept the input capacitor, inductor, and IC tightly coupled. It poured a small, dedicated copper island for the $V_{SW}$ node and placed the feedback divider resistors close to the IC's feedback pin, away from the inductor's magnetic field.

However, Quilter struggled with thermal polygon pours on the power plane. Rather than creating broad, uninterrupted copper polygons on Layer 3 for the 3.3V rail, it created a somewhat fragmented web of wide traces (30 to 50 mils). It worked electrically, and the DC drop was acceptable, but it resulted in unnecessary plane splits that compromised the return paths for non-power traces running on Layer 4.

Fab DRC and Manufacturing Yield

Getting a board to pass an internal DRC check inside EDA software is easy. Getting it to pass a fab shop's automated DFM without engineering queries (EQs) is harder.

We evaluated the output of both tools against standard JLCPCB and Eurocircuits manufacturing rules:

Minimum trace width / spacing: 5 mils / 5 mils (standard pool), 3.5 mils / 3.5 mils (advanced).
Minimum via hole size / diameter: 0.3 mm / 0.45 mm.
Solder mask expansion: 2 mils.
Minimum solder mask dam between pads: 4 mils.
Acid traps (acute copper angles under 90 degrees).

DFM Metric	DeepPCB (RL Routing)	Quilter (Physics Layout)	Manual Layout (Senior EE)
Acid Traps (<90 deg)	Frequent on dense pad exits	Rare; solver penalizes acute angles	Zero
Thermal Relief on Vias	Basic spoke rules; sometimes missing	Solid or 4-spoke configurable	Intentional based on copper mass
Via Density in Small Areas	High; clusters vias tightly	Balanced; spreads vias for return	Controlled; avoids Swiss-cheese ground
Solder Mask Dam Violations	None (uses footprint rules)	None (footprint dependent)	None
Copper Sliver Risk	Moderate near complex polygon pours	Low; cleans up narrow copper strips	Zero

DeepPCB occasionally generates acute angle trace junctions when it maneuvers around tight pad arrays on a 0.5 mm pitch QFN. These acute angles are classic acid traps. Modern etch processes at fabs like Eurocircuits handle these better than they used to, but fab review scripts will still flag them, delaying production.

Quilter's geometric solver is cleaner regarding trace geometry. It produces clean 45-degree chamfers and actively avoids narrow copper slivers. However, Quilter generates a higher total via count than an experienced human designer. On our test board, a senior designer routed the design using 42 vias. DeepPCB used 78 vias. Quilter used 112 vias.

More vias mean higher board capacitance, more interruptions to your ground plane, and higher drilling costs if you move from standard prototyping pools to high-volume production panels.

Where AI Autorouting Actually Saves Real Time

If you expect either of these tools to take a raw schematic and spit out production-ready Gerbers without engineering oversight, you will be disappointed. But treating them as useless is equally mistaken. For a solo hardware engineer, there is a sweet spot where these engines save significant time.

1. Escape Routing for High Pin-Count Microcontrollers

Escaping a 100-pin TQFP or a 144-pin BGA to the perimeter of the chip is purely mechanical work. You are simply trying to get traces from inner pads out to where they can be organized into buses.

DeepPCB is good at this. You can lock your power nets, lock your critical high-speed lines, select the MCU escape nets, and let the API solve the puzzle. It turns two hours of manual pad-nudging into a two-minute background process.

2. Low-Speed Digital and Housekeeping Signals

A typical mixed-signal board has dozens of uncritical nets: status LEDs, reset lines, enable signals, debug UARTs, I2C temperature sensors, and GPIO expanders. These run at low frequencies (under 1 MHz) with slow rise times.

Routing sixty housekeeping traces across a crowded board takes hours of manual point-to-point clicking. This is pure drudgery. Handing these specific nets to an autorouter while leaving critical analog, RF, and power sections locked is the most practical way to use these tools today.

3. Early Form-Factor Feasibility Checks

When a mechanical founder or industrial designer asks, "Can we fit this entire circuit into a 35 mm circular enclosure with a single 4-layer board?", you usually have to do a rough floorplan and spend half a day test-routing the densest section to give an honest answer.

Running the netlist through Quilter provides a quick sanity check. If Quilter cannot reach 100 percent completion on a 4-layer stackup with its solver running at full capacity, you can say with high confidence that the board needs a 6-layer stackup or a larger outline, without burning a full day of your own time.

The Hybrid Workflow for Solo Engineers

If you want to integrate automated routing into your workflow without causing unverified respins, you have to invert the traditional autorouting mentality. You do not design the board and then click "route all." You partition the design by physics first.

Step 1: Critical Floorplanning & Manual Placement
  │     (Connectors, MCU, Buck Regulators, Analog Frontend)
  ▼
Step 2: Manual Route Critical Power & High-Speed
  │     (Switch nodes, RF, USB diff-pairs, Decoupling Vias, Sensitive Analog)
  ▼
Step 3: Lock Routed Geometry in EDA
  │     (Freeze traces, vias, and copper islands)
  ▼
Step 4: AI Autorouting for Digital Glue
  │     (DeepPCB / Quilter / IntelCAD API runs on remaining non-critical nets)
  ▼
Step 5: Post-Route Inspection & Cleanup
        (Check plane return paths, via counts, acid traps, and DFM)

Phase 1: The Non-Negotiable Human Steps

Component Placement: Place your power converters, your decoupling capacitors, and your crystal oscillators manually. Keep the crystal within 5 mm of the MCU pins with an uninterrupted local ground underneath. No AI router currently balances crystal parasitic capacitance, stray clock coupling, and thermal gradients better than a careful engineer.
Critical Net Routing: Manually route your switch nodes, your analog sensing inputs, and your controlled-impedance differential pairs. Route them completely, add the required ground return stitching vias, and verify them.
Lock Everything Critical: In KiCad or Altium, select all the critical traces, vias, and polygons you just drew and lock them.

Phase 2: Delegating the Rest

Once the physics-critical elements are locked, export your design to the automated router. Whether you use DeepPCB's API integration, Quilter's solver, or automated net-class routers like IntelCAD, you let the engine tackle the remaining 60 to 70 percent of uncritical digital interconnects.

Phase 3: The 30-Minute Post-Routing Audit

When you pull the routed file back into your native EDA tool, never trust it blindly. Run this specific checklist:

Inspect Plane Integrity on Layer 2: Turn off all layers except Layer 2 (Ground). Look for spots where the autorouter dropped dense clusters of vias that cut the ground plane in half, creating narrow copper necks or slot antennas.
Check Decoupling Cap Routing: Verify that the autorouter did not route a VDD pin through a long 20-mil trace before reaching the decoupling cap's via. The path from the pin to the capacitor pad to the ground via must be as short and wide as possible to minimize parasitic inductance.
Look for Isolated Copper Islands: Autorouters often leave floating bits of copper or narrow peninsulas that are grounded at only one end. Either delete these copper slivers or stitch them with vias to prevent them from acting as patch antennas.
Run Native Fab DRC Rules: Do not rely on the AI's internal DRC. Load your fab's actual DRC profile (e.g., JLCPCB 4-layer 0.15mm trace/space rules or Eurocircuits standard pool rules) inside your EDA tool and run a fresh clearance check.

What to Watch For

The gap between DeepPCB (reinforcement learning on existing placement) and Quilter (generative placement and physics-based routing) highlights where EDA tooling is heading. Pure reinforcement learning is fast, but without deep physical simulation of electromagnetic fields, it will always require close supervision on mixed-signal boards. Physics-driven generative compilers like Quilter offer better physical validity, but require strict constraint definitions up front.

For engineers running hardware teams on tight budgets, these tools are useful if you treat them as assistants for escaping dense packages and finishing glue logic. The moment you treat them as an autonomous replacement for basic electromagnetic discipline, you will pay for it on the test bench.

Keep your high-speed return paths clear, manually route your buck converters, lock down your decoupling loops, and let the software push the rest of the traces.